LMARV-1 reboot part 14: Chips that don't exist

greetings risk five friends uh so today is going to be shorter than usual i'm not going to be actually doing any live work so you know there's going to be just a bunch of uh show and tell i guess um so you can see here um big schematic so this is what i've been working on over the past few weeks this is the sequencer base so if you want to know what that is just you know watch the previous videos um but i want to draw attention to some things here um let's open up this small section and we can see here this is actually a comparator and what i'm doing is uh i'm just checking the instruction for uh bad instructions and there are two defined bad instructions one of them is all zeros i think and one of them is all ones in the lower 16 bits or no one of them is all ones it says so right up here so one of them is all ones and the other one is all zeros in the low 16 bits and those are defined as bad instructions so um now in ttl there is a 74 uh 688 which is an eight bit uh equality comparator so you feed eight bits into it uh your eight bit signal and then your eight bit you know it could be a constant uh and it'll output whether they are equal or not unfortunately uh we are using lvc this is the low uh low voltage cmos the 3.3 volt version and there is no 3.3 volt version of the 8-bit equality comparator pretty much because of market forces um so there is a 688 it's just a 5-volt version in fact let me show you that let's see so here is the uh 8-bit magnitude slash identity comparator we're looking specifically at the 688 the 687 is the magnitude comparator and uh well we can see that it's a an ls and if you look through you know digikey or mouser this is all you get you don't get anything else and if we look down to the electrical characteristics yeah it's basically just a bunch of xors um we can see let's see if i can make this a little bigger great okay so uh supply voltage nominal 5 volts right min uh 150 millivolts below that max 250 millivolts above that so this is a 5 volt part it's not meant to operate at 3.3 volt you can't do it look at the input high and low level voltage so we have 2 is the minimum threshold for a high and .7 is the maximum threshold for a low now if you feed a 3.3 volt logic signal into this chip it will work because 3.3 volts come out and that's greater than two so there you go the input works and if you have a 3.3 volt chip that is 5 volt tolerant on its inputs then you could feed the outputs of this chip to that 3.3 volt chip and again things will work so this is one possibility is simply to use the 5 volt part let's take a look at the speed of this part though so if we go down here um it's it's okay i mean it's not bad um it it's showing what 12 maybe 17 nanoseconds um which is okay so that's certainly one possibility to consider um let's also again take a look at the schematic so this this was my solution um using only lvc parts so we have this open collector slash open drain um buffer the 07 is a buffer and the o6 is an inverter and i talked about this last time and basically you tie all the outputs together now because uh because this is open collector you do have to pull it up in case none of the outputs are um in case all of the outputs are open collector then the output is high instead of high impedance and then that gets fed to a gate over here so there was a comment basically saying yeah that's not going to work um and they were pretty much correct and let's see why so let me pull up the data sheet for the 1g32 okay so here is the datasheet for the 1g32 and first of all just for fun let's take a look at the propagation delay on it so propagation delay at 3.3 volts is typically 2.1 nanoseconds so it's fast um but what i really want to show is the input capacitance so it says five peak of farads so let's do some math um okay so what we have is uh our input and we have this going to 3v3 and it's 10k and it goes to the input of the chip which is five picofarads five picofarads let me use a a white marker okay so the input comes in over here so essentially this looks like this that's what an open collector output basically is either the switch connects the output to ground or the switch is open so uh if the switch is connected to ground then the capacitor is pretty much immediately discharged or you know as discharged as fast as uh current can be drawn into the chip um so that's pretty fast so we expect to see something like this uh how however when we open up the switch well the capacitor is going to charge through that resistor and then we're probably going to see you know something like this and the question is well when does it hit 2 volts because that's the threshold so let's do some calculations so there is the voltage and there is time and let me just think so the voltage is going to be equal to 3v3 times and then what i usually do to figure this out is i know that there's an e to the minus t over rc in here and what i do is i say okay what happens when t equals zero well when t equals zero e to the minus zero is just one so this is obviously wrong so i might need to put a three v three minus that whole thing in there sorry a one minus that in there that way when t equals zero e to the minus zero is one one minus one is zero so the voltage is zero and then as t goes to infinity well e to the minus infinity is just zero so three v three times one minus zero is three v three so this is the correct formula that's how i do it anyway i don't really memorize the formula i just sort of like you know remember what the factors are and then i just figure it out from there okay so um let's uh let's um say r is 10 times 10 to the 3 so that's 10k and c is 5 picofarads which is 5 times 10 to the minus 12 farads okay so we have v equals 3.3 times 1 minus e to the minus t over let's just multiply these out it's 50 times 10 to the minus 9. okay and i can just say 3.3 1 minus e to the minus t of to the minus so this is t times 0.02 times 10 to the ninth just inverting that so 150 is 0.02 10 to the minus 9 inverted is 10 to the ninth okay so we want to know when what time that's going to equal 2 volts so we have 2 equals this so i can divide by 3.3 equals 1 minus e to the t times 0.2 0.02 times 10 to the ninth okay so now i can [Music] take the e factor put it on one side and take this factor and put it on the other side just to get rid of the minus sign so e to the minus t 0.02 times 10 to the ninth equals 1 minus 2 over 3.3 whatever that is now i can take the natural log of both sides so we end up with minus t 0.02 times 10 to the ninth equals the natural log of this and then of course i'm just going to divide by negative 0.02 times 10 to the minus 9. i guess that was kind of stupid to do the inversion because now i just have to do it again so t equals negative 50 times 10 to the minus 9 times the natural logarithm of 1 minus 2 over 3.3 okay let me take out my trusty rpn calculator and work this out so we get 1 minus 2 over 3.3 take the natural log natural log it's negative so i take the negative of that multiply by 50 and times 10 to the minus 9 well that's just nanoseconds so this is equal to about 47 nanoseconds so there you go when the switch opens up it's going to take 47 nanoseconds for the for the voltage to be high enough for that gate to register as a one um so compared to like you know a gate that switches in two nanoseconds or even you know a gate that switches in 12 or 17 nanoseconds that's pretty slow so what i could do is i could make this 1k and the 1k is going to go into where the 1k is going to factor into here which basically means that i'm just going to go 10 times as fast so instead of 47 nanoseconds now it'll reach the threshold in 4.7 nanoseconds which is okay um there are some other complications like well you know we've got all these outputs tied together and when the switch opens um i don't think i think there's some like output capacitance that gets in the way so i really really really don't want to do this so yeah so that's uh that's the uh kind of the bad part of this so what i'm gonna have to do is go into the schematic and look at all the places that i did this and replace it with my chosen solution now i said that one of the solutions was just using the five volt part and because a lot of the three 3v3 parts that i use are 5 volt tolerant already i don't have to worry about doing voltage conversions the five volt part will happily take three v3 inputs and the three v3 parts will happily take five volt outputs so um so the other solution is something that was suggested let me just close this so this is the atf 1502 asv it is a 3.3 volt part and it is a cpld a complex programmable logic device so let's talk about those for a moment so let me get rid of all of this in the beginning there were pals and these were programmable array logic devices and what these were essentially the simplest ones were just what they call sum of products so the idea is that you would have inputs in in in and you would be able to select either the positive or the negative of each of the inputs so that's what that looked like and then you would have and terms and the and terms looked like this so you would get a bunch of n terms i'll just draw you know four a group of four and in between each of these intersections would be a fuse that you could that you could blow or connect the outputs of these so these these are what are called the and terms so i'm going to put a little and gate at the end of each of these and the idea is that for all the fuses that were blown here um those signals would be ended together so you could and you know the the um the positive of one input nothing from the second input the inverse of the first of the third input and so on and the the macro cell would be basically a group of those with an or gate at the end just like that and you could possibly um invert it so let's just put an inverter here and i don't know do this and that would be your output so in this way uh you could do a lot of different logical functions and you were basically only limited by the number of and gates that fed into an or gate and there were some pals which had more than others um then there were other pals which had registers at the end so you know there would be a a register here you know maybe we'll call it a a d flip-flop and there would be a clock line um and that would be your output you know or maybe it would be q naught would be your output you know one of those so um and that was pretty much the the extent of it um some pals even allowed you to fold back the uh the q outputs back into this array um you know with of course the negative uh so that you could sort of do little feedbacks and then you could you know make little counters or you know whatever so that was that uh then um and then the question is well okay how did you program it well you programmed it with with high voltages and they literally blew fuses in there um so they were one-time programmable otp one-time programmable so there were also for a brief period peels and these were programmable electrically erasable [Music] array logics okay so the idea here is that the fuses were not permanently blown so you could reset them electrically there were also ultraviolet uh versions of pals that you could actually erase by just putting them into an eprom eraser with ultraviolet light eventually there came the gal which was the generic array logic and the generic array logic survives today in the form of the atf 16v8 no i don't think they make those anymore uh the 22v10 they definitely make and i think that's probably all you could get there may be a 20v8 what this what the numbering system means is that you have 22 ios and you can have 10 of those being inputs as many as 10. uh same same thing here you have 20 ios well okay obviously they're not ios um yeah okay so so there are 20 ios not all of them are outputs uh maybe the eight is the number of outputs that you get i think that's what it is yeah right that's what it is so for the uh for the 22v10 there are 22 um pins 10 of which maximum can be outputs they can all be inputs uh and basically it's the the usual sum of products array with registers on the end that are optional with optional clear optional preset i think there's a clock there's an output enable so there's a bunch of options for for each of these so-called macro cells so the 22v10 has 10 macrocells the 20v8 has 8 macrocells and that's basically that so after the gal um was wildly successful then there came ever more complex devices so cplds are kind of next on the scale of complexity these are the complex programmable programmable logic devices and for the most part they're sort of like gals except they they're kind of bigger they have more features um and that's what the atf 1502 1504 and 1508r and that is the thing that i want to look at what's next uh the fpga the field programmable gate array so this is like you know the sea of macro cells that have you know very complex routes between them and you know all sorts of i o options and you know it's like complex squared so uh so let's take a look at this uh cpld so let me show this thing again okay so here's an example of a macro cell so we can see that there are these five and terms and these are the same thing um you can see here uh there's this little buffer si sin symbol with a bubble so this is you know you can select the positive or the negative of this and there are basically 80 lines that go across so you have uh 80 signals that's 40 signals plus their inverts and you can add them all together and and here are these fold backs as well there's one fold back here there's a they don't call it a fold back but they call it a feedback this comes from an io pin so this is an input this comes from say the output of this xor gate or the output of this flip-flop and it can go back into the global bus so basically you can select any of those you can and them together and then your function is programmed using fuses your your sum of products is programmed using fuses and then there are the options in the macro cell so here's an example here's a view of the plcc version and this is the tqfp version they have different pin outs they're actually rotated so you can see the ios around the edge okay this is the macro cell itself not the macrocell this is this is the overall view of the chip so you've got these buses you've got a bunch of macro cells organized into blocks for the atf 1502 there are 16 macro cells in block a and 16 macro cells in block b so that's 32 macro cells so um so at a maximum that would be 32 computed outputs as compared to like the 10 that you would get in the 22v10 so this is obviously a bigger device um okay and they don't actually tell you how to program it because that's the secret squirrel sauce um however however uh white cork has put together a github repository uh which actually uh explored what the fuses did because what you can do is you could take their crappy you could take um microchip's crappy uh bitstream generation program um and you can create bit streams out of it or um you could take the bit stream and you can start flipping bits and then just sort of analyzing what happens to the chip um and uh in this way uh white quark was able to determine what fuses did what and i also made a bunch of diagrams to show what fuses do what so now we have a way to program these chips using open source software so things like um nmygen and and yosis and um you know python and that sort of thing without having to go through the crappy windows only software which crashes all the time there are some limitations though you can get as far as defining the logic and then there's a gap and then there's how to convert that logic into fuses uh that results in a file that you can then um write to the chip using a standard uh jtag connector so there's that little gap that we have to that we have to jump so let me show you how i'm going to do that so now i can finally show you this thing all right so this thing right here is a diagram of the 181 alu this is the first chip that i wanted to tackle because it would be probably the most complex chip that um that i would want to convert into a cpld oh and in terms of what i'm what my self-imposed rules allow me to put on these cplds so um so you know that i've been using these you know one gate chips so my input my self-imposed rules are if something is rom-like then i can wait if something is a very large lookup table with lots of inputs and lots of outputs and they aren't separable then i can convert that into a rom if something is a logic chip that should exist but doesn't because of market forces then i am allowed to to substitute that one for one for a cpld so here's an example right here the 181 is an alu chip it's not available in 3v3 form but if market forces were slightly different and people were still using the 181 well there would be a 74 lvc 181 there just doesn't happen to be one so according to my rules i'm allowed to take one 181 chip convert it into logic and program it into one cpld i'm not allowed to put any extra logic into the cpld i'm only allowed to implement the logic of this one chip i'm not allowed to take say two 181s and stuff them into a single chip so those are my self-imposed rules uh so in effect i'm basically saying well if there were a 3v3 version of the 181 this chip would be it so so that's that um anyway in the data sheet of the 181 they're very nice they very nicely laid out the logic of these chips now if we look at this closely you can kind of see that there are various levels here so here we go so this is one level and you can recognize this as a sum of products yes there's an inverter on the end but basically there are all the and gates here is some of the inputs are inverted and there are the or gates so um in the cpld this is basically one macro cell right here so we have one two three four five six seven eight eight of them now these xors um although there are xors in the macro cells unfortunately it's not easy to just you know take the or gate plug it directly into the xor and then take another input and plug that into the xor it can be done but it's a lot easier if you have the space to just reserve one macro cell whose function is only an xor so that's one two three four more macro cells okay so what's our total 12 okay now we can see that the next level is again a bunch of sum of products so here's a here's a product with really no sum so it's one sum right so there's one two three four there's five and there's six and there's seven so we're up to what is it 19 now i think then there are a bunch of more uh xors so that's 20 21 22 23 um here's another macro cell so that's 24 and here's the final macro cell so that's 25. all right well we have 32 macro cells in our chip and we've used 25 so it should work um i'm not using any registers so i don't have to bother about that complication so uh what i did was i was able to determine um that if i could program this in mygen and basically uh program each l each layer one by one uh there's a bunch of commands that you can use to generate a sum of products and it looks something like this let's see if i can pull this up so yeah okay so here's an example of a pla file um and a pla file basically specifies your inputs your outputs and the sum of products so each one of these columns down here these things okay each one of those columns is one of these outputs so the first bit here is your n carry out the second bit here is your a equals b and the idea is that um the and terms are all the ones or together and these are your inputs the dashes or don't cares so in this particular case n carryout consists of this one input needs to be zero or this other input needs to be zero and you know if you look at this gate right over here well that's exactly what it is this one input is zero this other input is zero or them together that's your output so i wrote a parser for this pla right and again the pla file only represents sum of products that's it um let's see do i have another one okay so this is a special pla file that i wrote and i added this special function called dot xor which basically says this is not a sum of products this is an xor um and basically what i did was i said okay well the xor is basically the the one in this column and these are the two inputs that's all you get because that's all i ever needed so now i have pla files and i'll i'll talk about converting nmigen into the pla files in a moment so now you have a bunch of pla files and we can look over here to see how we can actually layer these so you've got a bunch of inputs and then you have a an and or a layer that's your sum of products then the next layers is optionally a bunch of ands but basically the xor so you can get the outputs of the previous layer and also any inputs and then you just basically layer them until you reach the outputs and then you are done so i wrote a program that takes in all of these pla files and basically uses the fuse database that white quark has published in uh in the github which i will if i can remember have a link to below and basically converts it to an entire fuse map that i can then burn onto the chip using a jtag programmer so now the question is well okay so how do you get from nmigen to the pla file so let's open up the code again and go to um i'm having a bunch of glare on the screen okay that's a little better ics.pi okay so let's go to here so we can see here that this is and or layer one so here are the inputs these are just the chips inputs or most of them and basically this is the logic of uh the first layer okay and then i have this method called two rtl it doesn't do any formal verification all it does is elaborate the module and convert it to rtl okay once it's in rtl format how do we get it into pla format so let's see if i can show that let me pull up a window all right here we go so let's go to mntf um so basically what i do is um risk five reboot so what i do is i run okay so what have i got as the main for this file right now okay i've got and or layer three that's fine we'll do and or layer three so what i do is i run ics.pi in rtl mode and what that does is it gives me this top level dot il file so the first thing that you do the first thing that you do is you run it through [Music] what do you do you run it through yosis with this command line minus p synth minus o and then a blip file which i think stands for block level information file or something like that and you give it top level top level dot il so it goes ahead and it does something again i'm not really sure what the blip file has in it but if you look at it it has something to do with the logic okay so there's there's some stuff in there the next thing that you do is you run yosis abc and what you do is you do read read blip so you read the blip file 181 l3 not blip and then you call collapse what collapse does is it turns it into a sum of products and then you write pla i'm just going to write a dot pla and then you can exit or you can quit okay so if we look at a.pla well that's the pla file that we saw before so the other uh the xor layers um i just you know wrote it myself because it's you can see that the format is pretty straightforward there's also an output layer so if we look at uh 181 out dot pla what i did was i said okay let's just define this this parameter called dot outputs that basically says all of these output blocks those are the output of the chip those are the outputs of the chip and that's it so i wrote a python program to basically read all these files in and convert them to a fuse map um the way you convert it into a fuse map is that there's a utility that white cork wrote that uh will take a template file which is essentially a blank file for uh an 1502 chip it's a blank fuse file and then you basically say you know set this fuse set that fuse and it's uh it's nice because it's symbolic so you can say you know set this fuse name or this macro cells feature to that setting and basically my python program just outputs those settings those set commands um the result is a file that you can then program using jtag um and that's it now i haven't actually done that yet but that's that's the next stage so so with that what i decided to do is to take the 181 and convert it into a cpld and i also want to take the 688 and convert it into a cpld as well and then i can just pop that into the circuit instead of you know doing this this crazy stuff that i've been doing that probably won't work anyway um yeah and that's really all i wanted to talk about today so like i said bit of short video you know not much live programming or live schematicing or anything like that but um this is a a decision that i've made and uh that's uh what's going to happen uh going forward now hopefully uh by next week i will have all the hardware that i need to actually program one of these cplds and test it uh so we can see that it is actually doing uh either the alu functionality or the uh the comparison functionality and then we can use those in our schematic so i guess that's it for now um thanks for watching and i hope to see you all next week bye